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PRELIMINARY
CY7C53120L8 CY7C53150L
3.3V Neuron(R) Chip Network Processor
Features
* 3.3V operation * Three 8-bit pipelined processors for concurrent processing of application code and network traffic * Four-pin hardware SCI/SPI interface * Eleven-pin I/O port programmable in 34 modes for fast application program development * Two 16-bit timer/counters for measuring and generating I/O device waveforms * Five-pin communication port that supports direct connect and network transceiver interfaces, and operates at 3.3V or 5V * Programmable pull-ups on IO4-IO7 and 20-mA sink current on IO0-IO3 * Unique 48-bit ID number in every device to facilitate network installation and management * 0.35-m Flash process technology * On-chip LVD circuit with programmable trip point * Programmable Pulse Stretching reset * 4,096 bytes of SRAM for buffering network data, system, and application data storage * 512 bytes (CY7C53150L), 8KB (CY7C53120L8) of Flash memory with on-chip charge pump for flexible storage of configuration data and application code * Addresses up to 58 KB of external memory (CY7C53150L) * 12 KB (CY7C53120L8) of ROM containing LonTalk network protocol firmware * Maximum input clock operation of 20 MHz (CY7C53120L8/3150L) over a -40C to 85C[1] temperature range * 64-pin and 100-pin TQFP package (CY7C53150L) * 32-pin SOIC or 44-pin TQFP package (CY7C53120L8) Logic Block Diagram Media Access Control Processor Network Processor Application Processor 4-KB RAM Flash ROM (CY7C53120L8) Internal Data Bus (0:7) Internal Address Bus (0:15)
Functional Description
The 3.3V Neuron chip (CY7C53120L8/3150L) is a low-power version of the 5V Neuron chip with a number of feature enhancements. The CY7C53120L8/3150L Neuron chip implements a node for LonWorks distributed intelligent control networks. It incorporates, on a single chip, the necessary communication and control functions, both in hardware and firmware, that facilitate the design of a LonWorks node. The CY7C53120L8/3150L supports all the functionality of the 5V CY7C531x0 Neuron chip. Additionally it features 4 KB of RAM, 8KB of Flash memory (CY7C53120L8), and hardware SCI/SPI. The CY7C53120L8/3150L has an 11-pin configurable I/O block. The I/Os are all 5V-tolerant to allow interfacing to other 5V components and microcontrollers. The CY7C53120L8/3150L contains a very flexible five-pin communication port that can be configured to interface with a wide variety of media transceivers at a wide range of data rates. The communication port can operate at either 3.3V or 5V. In 5V mode the transceiver is completely backward compatible with existing 5V transceivers. The most common transceiver types are twisted-pair, powerline, RF, IR, fiber-optics, and coaxial. The CY7C53150L incorporates an external memory interface that can address up to 64 KB with 6 KB of the address space mapped internally. LonWorks nodes that require large application programs can take advantage of this external memory capability. Services at every layer of the OSI networking reference model are implemented in the LonTalk firmware-based protocol stored in 12-KB ROM (CY7C53120L8), or off-chip memory (CY7C53150L). The firmware also contains 34 preprogrammed I/O drivers, simplifying application programming. The application program is stored in the Flash memory (CY7C53120L8) and/or off-chip memory (CY7C53150L), and may be updated by downloading over the network. Communications Port Two Timer/Counters 4-pin SCI/SPI I/O Block Oscillator, Clock, and Control CLK1 CLK2 SERVICE RESET IO10 : IO7 IO6 : IO0 CP4 CP0
External Address and Data Bus (CY7C53150L)
Note: 1. Maximum junction temperature is 105C. TJunction = TAmbient + V*I*JA. 32-pin SOIC JA = 51C/W. 44-pin TQFP JA = 43C/W. 64-pin TQFP JA = 44C/W. 100-pin TQFP JA = 49.2C/W.
Cypress Semiconductor Corporation Document #: 38-10002 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised March 21, 2003
PRELIMINARY
CY7C53150L 100-lead Thin Quad Flat Pack
[2] [2] [2] [2] [2] [2] [2]
VDD A10 A12 A13
CY7C53120L8 CY7C53150L
[2]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC[2] IO0 IO1 IO2 IO3 VSS RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65
A14
VSS
A11
NC
NC
NC
NC
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
[2] [2] [2] NC
NC NC A15 NC E R/W VDD D0 NC D1 VDD D2 D3 NC D4 D5 NC D6 D7 NC NC
VSS
[2]
[2] [2] NC [2] NC
NC VPP IO4 IO5 IO6 VSS VDD
[2]
CY7C53150L-100AI
64 63 62 61 60 59 58 57 56 55 54 53 52 51
[2]
[2] NC [2] NC
SS/IO7 NC
[2]
[2]
VDD SCLK/RXD/IO8 NC NC
[2] [2]
[2] [2]
CP4 CVSS
MISO/IO9
CVDD
CLK2
CLK1
CP0
CP1
CP2
MOSI/TXD/IO10
[2] NC
[2] NC
[2] NC
CP3
VSS
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
NC SERVICE
NC
NC
NC
NC
NC
NC
NC
NC
NC
Note: 2. No Connect (NC) -- should not be used. (These pins may be used for internal testing.)
Document #: 38-10002 Rev. *B
NC
NC
[2]
Page 2 of 16
PRELIMINARY
CY7C53150L 64-lead Thin Quad Flat Pack
NC[2] A15 E R/W VDD D0 D1 VDD VDD VSS D2 D3 D4 D5 D6 D7
CY7C53120L8 CY7C53150L
NC[2] A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 24 57 CY7C53150L-64AI 23 58 22 59 21 60 20 61 19 62 18 63 17 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CP4 CP3 CP2 CP1 CP0 NC[2] CVDD CVSS CLK1 CLK2 VDD VSS VDD VSS NC[2] SERVICE
Vss Vpp IO4 IO5 IO6 SS/IO7 SCLK/RXD/IO8 MISO/IO9
Note: 3. The smaller dimple at the bottom left of the marking indicates pin 1.
Document #: 38-10002 Rev. *B
MOSI/TXD/IO10
IO0 IO1
IO2 IO3 RESET VDD
NC[2]
Pin 1 Indicator [3]
Page 3 of 16
PRELIMINARY
44-lead TQFP IO10/MOSI/TXD IO8/SCLK/RXD
CY7C53120L8 CY7C53150L
IO9/MISO
IO7/SS
NC[2]
NC[2]
32-lead SOIC RESET VDD IO4 IO3 IO2 IO1 IO0 SERVICE VSS Vpp VDD VDD VSS CLK2 CLK1 CVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD VSS IO5 IO6 IO7/SS IO8/SCLK/RXD IO9/MISO VDD IO10/MOSI VSS CP4 CP3 CP1 CP0 CVDD CP2 33 32 31 30 29 28 27 26 25 24 23
NC2]
CP4
CP3
VDD
VSS
NC[2] IO6 IO5 VSS VDD NC
[2]
34 35 36 37 38 39 40 41 42 43 44 10 1 11 2 3 4 5 6 7 8 9 CY7C53120L8-44AI
22 21 20 19 18 17 16 15 14 13 12
NC[2] CP1 CP0 CVDD CP2 NC[2] CVSS CLK1 CLK2 VSS NC[2]
CY7C53120L8-32SI
RESET VDD IO4 IO3 NC[2]
NC[2]
NC[2]
Pin Descriptions
Pin Name CLK1 CLK2 Input Output I/O Pin Function Oscillator connection or external clock input. Oscillator connection. Leave open when external clock is input to CLK1. Maximum of one external load. Reset pin (active LOW). Note. The allowable external capacitance connected to the RESET pin is 100-1000 pF. Service pin (active LOW). Alternates between input and output at a 76-Hz rate. Large current-sink capacity (20 mA). General I/O port. The output of timer/ counter 1 may be routed to IO0. The output of timer/counter 2 may be routed to IO1. CY7C53150L CY7C53150L CY7C53120L8 TQFP-100 TQFP-64 SOIC-32 Pin No. Pin No. Pin No. 35 34 24 23 15 14 CY7C53120L8 TQFP-44 Pin No. 15 14
RESET
I/O (Built-In Pull-up)
7
SERVICE
6
1
NC[2]
IO2
IO1
IO0
VSS
Vpp
VDD
VDD
PIN 1 INDICATOR
40
SERVICE I/O (Built-In Configurable Pull-up) IO0-IO3 I/O
30
17
8
5
2, 3, 4, 5
2, 3, 4, 5
7, 6, 5, 4
4, 3, 2, 43
Document #: 38-10002 Rev. *B
Page 4 of 16
PRELIMINARY
Pin Descriptions (continued)
Pin Name IO4-IO7 I/O I/O (Built-In Configurable Pull-ups) Pin Function
CY7C53120L8 CY7C53150L
CY7C53120L8 TQFP-44 Pin No. 42, 36, 35, 32
CY7C53150L CY7C53150L CY7C53120L8 TQFP-100 TQFP-64 SOIC-32 Pin No. Pin No. Pin No. 3, 30, 29, 28
General I/O port. The input to 12, 13, 14, 19 10, 11, 12, 13 timer/counter 1 may be derived from one of IO4-IO7. The input to timer/counter 2 may be derived from IO4. General I/O port. May be used for serial communication under firmware control. Slave Select. Muxed with IO7. SPI Clock or SCI RXD. Muxed with IO8. Can be configured as Open Drain Output. SPI Master In/Slave Out (MISO) Muxed with IO9. Can be configured as Open Drain Output. SPI Master out/Slave In (MOSI) or SCI TXD. Muxed with IO10. Can be configured as Open Drain Output. 22, 25, 28 14, 15, 16
IO8-IO10 I/O (Programmable current drive) SS Input SCLK/RX I/O D MISO I/O
27, 26, 24
31, 30, 27
19 22
13 14
28 27
32 31
25
15
26
30
MOSI/TX I/O D
28
16
24
27
D0-D7 R/W E A0-A15
I/O Output Output Output
Bidirectional memory data bus. 66, 64, 62, 61, 43, 42, 38, 37, 59, 58, 56, 55 36, 35, 34, 33 Read/write control output for external memory. Enable clock control output for external memory. Memory address output port. 68 69 98, 97, 96, 95, 94, 93, 91, 90, 86, 85, 83, 82, 80, 78, 76, 71 45 46 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 47 7, 20, 22, 40, 41, 44 8,19, 21, 39
N/A N/A N/A N/A
N/A N/A N/A N/A
VDD
Input
Power input (3.3V nom.). All VDD 16, 21, 63, 88, pins must be connected together 67 externally. Power input (0V, GND). All VSS pins must be connected together externally. Power input, 5V or 3.3V depending on Communications Port Voltage. Power input (0V GND). In-circuit test mode control. If VPP is high when RESET is asserted, the I/O, address and data buses become Hi-Z. 6, 15, 26, 75, 100 37
2, 11, 12, 25, 32 9, 13, 23, 31
9, 10, 29, 38, 41 7,13, 26, 37
VSS CVDD [4]
Input
Input
26
18
19
CVSS VPP
Input Input
51 11
25 9
16 10
16 8
Note: 4. In case the Comm port is used at 5V, CVDD = 5V can not be applied before VDD has stabilized.
Document #: 38-10002 Rev. *B
Page 5 of 16
PRELIMINARY
Pin Descriptions (continued)
Pin Name I/O Pin Function
CY7C53120L8 CY7C53150L
CY7C53120L8 TQFP-44 Pin No.
CY7C53150L CY7C53150L CY7C53120L8 TQFP-100 TQFP-64 SOIC-32 Pin No. Pin No. Pin No.
CP0-CP4 CommuniBidirectional port supporting cation Network communications in three Interface modes. NC - No connect. Must not be connected on the user's PC board, since they may be connected internal to the chip.
41, 43, 46, 49, 28, 29, 30, 31, 19, 20, 17, 21, 22 20, 21, 18, 24, 53 32 25 1, 8, 9, 10, 17, 1, 18, 27, 48, 18, 20, 23, 24, 49 27, 29, 31, 32, 33, 36, 38, 39, 40, 42, 44, 45, 47, 48, 50, 52, 54, 57, 60, 65, 70, 72, 73, 74, 77, 79, 81, 84, 87, 89, 92, 99 - 1, 6, 11, 12, 17, 22, 23, 28, 33, 34, 39, 44
Memory Usage
All Neuron chips require system firmware to be present when they are powered up. In the case of the CY7C53120L8, this firmware is preprogrammed in the factory in an on-chip ROM. In the case of the CY7C53150L, the system firmware must be present in the first 16 KB of an off-chip nonvolatile memory such as Flash, EPROM, EEPROM, or NVRAM. Because the system firmware implements the network protocol, it cannot itself be downloaded over the network. For the CY7C53120L8, the user application program is stored in on-chip Flash memory. It may be programmed using a device programmer before board assembly, or may be programmed in-circuit after board assembly through a proprietary 10-pin programming interface or over the LonTalk network from an external network management tool. For the CY7C53150L, the user application program is stored in on-chip Flash Memory and also in off-chip memory. The user program may initially be programmed into the off-chip memory device using a device programmer.
Ability to switch to fast programming is provided if an LVI trip occurs while programming the flash. This improves the reliability of the chip in case of sudden power failure.
Low-Voltage Inhibit (LVI) Operation
The on-chip Low-voltage Inhibit circuit trips the Neuron chip reset circuit whenever the VDD input drops below a programmable value between 2.7V and 3.05V. The purpose of this feature is to prevent the corruption of nonvolatile memory during voltage drops. The default value of the LVI trip point is 2.7V. A lower value of trip point voltage decreases the likelihood of the LVI tripping due to noise on VDD. A lower setting is therefore recommended for circuits with a lot of noise on the power supply. In circuits that do not have excessive noise it is recommended that the LVI trip point be increased which results in better flash protection in case of real power loss scenarios. The LVI also features a programmable digital filter used to filter out VDD noise. This is another method of decreasing the possibility of the LVI being triggered by the noise as opposed to true power loss events. The digital filter is programmed to a value between 16 and 128 clock cycles. The value chosen depends on the frequency of the VDD noise where the digital filter period should slightly exceed the minimum frequency noise seen on VDD. The LVI digital filter defaults to 128 clock cycles.
Flash Memory Retention and Endurance
Data and code stored in Flash Memory is guaranteed to be retained for at least ten years for programming temperature range of -40C to 85C. The Flash memory can typically be written 100,000 times without any data loss[5]. An erase/write cycle takes 20 ms. The system firmware extends the effective endurance of the Flash memory in two ways. If the data being written to a byte of Flash memory is the same as the data already present in that byte, the firmware does not perform the physical write. So for example, an application that sets its own address in Flash memory after every reset will not use up any write cycles if the address has not changed. In addition, system firmware version 13 or higher is able to aggregate writes to eight successive address locations into a single write for CY7C53120L8 devices. For example, if eight KB of code is downloaded over the network, the firmware would execute only 1024 writes rather than 8,192.
Reset Stretching
At Power-on, the CY7C53120L8/3150L provides internal Reset Stretching of 50ms minimum at 10MHz clock frequency. Power-on Reset Stretch time scale with frequency. After Power-on, Reset Stretch is 50ms independent of frequency of operation. At Power-on the CY7C53120L8/3150L defaults to Reset Stretch enabled. The Reset Stretch can either be left enabled or disabled through software. Reset Stretching eliminates the need for an external pulse stretching LVI which is required when using the 3150L with an external Flash memory.
Note: 5. For detailed information about data retention after 100K cycles, please see Cypress qualification report.
Document #: 38-10002 Rev. *B
Page 6 of 16
PRELIMINARY
Hardware Serial Communication (SPI/SCI) Engine
The CY7C53120L8/3150L features a hardware Serial Communication Engine. The hardware engine is capable of performing high-speed communications in either SPI or SCI more. Serial Peripheral Interface (SPI) Mode SPI mode is 4-pin synchronous serial communications interface that can be set as either a Master or a Slave. SPI Pin Definition Pin IO7 IO8 IO9 IO10 Slave Select (SS) Hardware SPI Serial Clock (SPSCK) Master Input/Slave Output (MISO) Master Output/Slave Input (MOSI) Function
CY7C53120L8 CY7C53150L
Serial Communication Interface (SCI) Mode
SCI mode provides a full-duplex asynchronous NRZ format serial interface for communicating with other devices with either an SCI or UART interface. The SCI interface is optimized to provide industry standard UART baud rates from the CY7C53120L8/3150L crystal clock rates. SCI Pin Definitions Pin IO8 IO10 Function Receive Data (RXD) Transmit Data (TXD)
SPI communication is a point-to-point or point-to-multi-point interface that can be configured as master/slave, singlemaster/multiple-slaves or multiple-masters/single-slave. The master initiates all communication between slave and master. The master drives the SPSCK signal, which is a clock used to synchronize all data communication between master and slave. Slave Select (SS) is an input to the Neuron chip in both the Master and the Slave modes. In Slave mode, SS is active low with the Slave communicating only when SS is low. In Master mode, the SPI engine functions only when the SS signal is held high. SS can be hard wired high or low or it can be wired to signals being generated from other sources. The Neuron Chip can use IO0 through IO6 for selecting between multiple slaves when acting as a master. MOSI and MISO are used to send and receive data over SPI. MOSI is a data output in Master mode and is an input in Slave mode. MISO is an input in Master mode and is an output in Slave mode. The phase and polarity of the data relative to the clock signal is programmable and can be configured in four possible modes. The SPI interface can communicate at a maximum 2.5-Mbps data rate (10-MHz input clock frequency). The data rate is programmable and can be scaled by selecting the desired divisor ranging from 2 to 256 in multiples of 2.
RXD is used to receive serial data at the specified baud rate. TXD is used to transmit data serially at the specified baud rate. The idle state of the TXD and RXD lines is high. All data bytes begin with a start bit which is a `0'; this is followed by eight or nine bits of data, LSB first, and end with a stop bit which is a return to the idle state of `1.' The number of bits transmitted or received is programmable between eight or nine bits. The ninth bit can be used as a parity bit or as a second stop bit. The maximum baud rate for the SCI engine is 460.8 Kbaud (10-MHz input clock frequency). The SCI can be programmed to run at most standard UART baud rate values.
Communications Port
The Neuron chip includes a versatile 5-pin communications port that can be configured in three different ways. The Communications port can operate at either 3.3V or 5V. The Communication port can be made backward-compatible with existing 5V transceivers by supplying a 5V supply to the CVDD pin. In Single-ended Mode, pin CP0 is used for receiving serial data, pin CP1 for transmitting serial data, and pin CP2 enables an external transceiver. Data is communicated using Differential Manchester encoding. In Special Purpose Mode, pin CP0 is used for receiving serial data, pin CP1 for transmitting serial data, pin CP2 transmits a bit clock, and pin CP4 transmits a frame clock for use by an external intelligent transceiver. In this mode, the external transceiver is responsible for encoding and decoding the data stream. In Differential Mode, pins CP0 and CP1 form a differential receiver with built-in programmable hysteresis and low-pass filtering. Pins CP2 and CP3 form a differential driver. Serial data is communicated using Differential Manchester encoding. The following tables describe the communications port when used in Differential Mode.
Document #: 38-10002 Rev. *B
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PRELIMINARY
CP0 - CP1
Vhys + 200 mV CP0 VDD/2 CP1
CY7C53120L8 CY7C53150L
Programmable Hysteresis Values (5V) (Expressed as differential peak-to-peak voltages in terms of VDD) Hysteresis[6] 0 1 2 3 4 5 6 7 Vhys Min. 0.019 VDD 0.040 VDD 0.061 VDD 0.081 VDD 0.101 VDD 0.121 VDD 0.142 VDD 0.162 VDD Vhys Typ. 0.027 VDD 0.054 VDD 0.081 VDD 0.108 VDD 0.135 VDD 0.162 VDD 0.189 VDD 0.216 VDD Vhys Max. 0.035 VDD 0.068 VDD 0.101 VDD 0.135 VDD 0.169 VDD 0.203 VDD 0.236 VDD 0.270 VDD
3 ns
Figure 1. Receiver Input Waveform Programmable Hysteresis Values (3.3V) (Expressed as differential peak-to-peak voltages in terms of VDD) Hysteresis[6] 0 1 2 3 4 5 6 7 Vhys Min. 0.019 VDD 0.038 VDD 0.057 VDD 0.076 VDD 0.095 VDD 0.114 VDD 0.133 VDD 0.152 VDD Vhys Typ. 0.027 VDD 0.054 VDD 0.081 VDD 0.108 VDD 0.135 VDD 0.162 VDD 0.189 VDD 0.216 VDD Vhys Max. 0.035 VDD 0.070 VDD 0.105 VDD 0.140 VDD 0.175 VDD 0.210 VDD 0.245 VDD 0.280 VDD
Programmable Glitch Filter Values[7](Receiver (end-to-end) filter values expressed as transient pulse suppression times) Filter (F) 0 1 2 3 Min. 10 120 240 480 Typ. 75 410 800 1500 Max. 140 700 1350 2600 Unit ns ns ns ns
Receiver[8] (End-to-End) Absolute Asymmetry (Worst-case across hysteresis) Filter (F) 0 1 2 3 Max (tPLH - tPHL) 35 150 250 400 Max (tPLH - tPHL) 24 Unit ns ns ns ns
Differential Receiver (End-to-End) Absolute Symmetry[9, 10] Filter (F) Hysteresis (H) 0 0 Unit ns
Electrical Characteristics (VDD = 3.0V-3.6V)
Parameter VDD VIL Power Supply Voltage Input Low Voltage IO0-IO10, CP0, CP3, CP4, SERVICE, D0-D7, RESET CP0, CP1 (Differential) Input High Voltage IO0-IO10, CP0, CP3, CP4, SERVICE, D0-D7,RESET CP0, CP1 (Differential) Low-Level Output Voltage Iout < 20 A Standard Outputs (IOL = 1.4 mA)[11] High Sink (IO0-IO3), SERVICE, RESET (IOL = 20 mA) High Sink (IO0-IO3), SERVICE, RESET (IOL = 10 mA) Maximum Sink (CP2, CP3) (IOL = 40 mA) Maximum Sink (CP2, CP3) (IOL = 15 mA) Description Min. 3.0 -- -- 2.0 Programmable -- -- -- -- -- -- Typ. 3.3 -- -- -- -- -- -- -- -- -- -- Max. 3.6 0.8 Programmable V -- -- V 0.1 0.4 0.8 0.4 1.0 0.4 Unit V V
VIH
VOL
Notes: 6. Hysteresis values are on the condition that the input signal swing is 200 mV greater than the programmed value. 7. Must be disabled if data rate is 1.25 Mbps or greater. 8. Receiver input, VD = VCP0 - VCP1, at least 200 mV greater than hysteresis levels. See Figure 1. 9. CP0 and CP1 inputs each 0.60 Vp - p, 1.25 MHz sine wave 180 out of phase with each other as shown in Figure 8. VDD = 5.00 V 5% (VDD = 3.30 V 5%). 10. tPLH: Time from input switching states from low to high to output switching states. tPHL: Time from input switching states from high to low to output switching states.
Document #: 38-10002 Rev. *B
Page 8 of 16
PRELIMINARY
Electrical Characteristics (VDD = 3.0V-3.6V) (continued)
VOH High-Level Output Voltage Iout < 20 A Standard Outputs (IOH = -1.4 mA)[11] High Sink (IO0 - IO3), SERVICE (IOH = -1.4 mA) Maximum Source (CP2, CP3) (IOH = -40 mA) Maximum Source (CP2, CP3) (IOH = -15 mA) Hysteresis (Excluding CLK1) Input Current (Excluding Pull-Ups) (VSS to VDD) Operating Mode Supply Current 20-MHz Clock 10-MHz Clock 5-MHz Clock 2.5-MHz Clock 1.25-MHz Clock 0.625-MHz Clock[14] Sleep Mode Supply Current[13]
[13] [12]
CY7C53120L8 CY7C53150L
V VDD - 0.1 VDD - 0.4 VDD - 0.4 VDD - 1.0 VDD - 0.4 175 -- 60 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 260 21 13 8 5 3 2 10 A mV A A mA
Vhys Iin Ipu IDD
Pull-Up Source Current (Vout = 0 V, Output = High-Z)[12]
IDDsleep
LVI Trip Point (VDD)
Part Number CY7C53120L8, and CY7C53150L Min. 2.7 Programmable Max. 3.05 Unit V
External Memory Interface Timing -- CY7C53150L, VDD 10% (VDD = 3.0V to 3.6 V, TA = -40C to+ 85C[1])
Parameter tcyc PWEH PWEL tAD tAH tRD tRH tWR tWH tDSR tDHR tDHW tDDW tDHZ tDDZ tacc Pulse Width, E High[16] Pulse Width, E Low[16] Delay, E High to Address Valid Address Hold Time After E High Delay, E High to R/W Valid Read R/W Hold Time Read After E High Delay, E High to R/W Valid Write R/W Hold Time Write After E High Read Data Setup Time to E High Data Hold Time Read After E High Data Hold Time Write After E High[17, 18] Delay, E Low to Data Valid Data Three State Hold Time After E Low[19] Delay, E High to Data Three-State[18] External Memory Access Time (tacc = tcyc - tAD - tDSR) at 10-MHz input clock Description Memory Cycle Time (System Clock Period)
[15]
Min. 200 tcyc/2 - 5 tcyc/2 - 5 -- 10 -- 5 -- 5 15 0 10 -- 0 -- 150
Max. 3200 tcyc/2 + 5 tcyc/2 + 5 35 -- 25 -- 25 -- -- -- -- 12 -- 42 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 11. Standard outputs are IO4-IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < 15 pF load.) For CY7C53150L, standard outputs also include A0-A15, D0-D7, E, and R/W. 12. IO4-IO7 and SERVICE have configurable pull-ups. RESET has a permanent pull-up. 13. Supply current measurement conditions: VDD = 3.3V, all outputs under no-load conditions, all inputs < 0.2V or > (VDD - 0.2V), configurable pull-ups off, crystal oscillator clock input, differential receiver disabled. The differential receiver adds approximately 200 A typical and 600 A maximum (at 5V) when enabled. It is enabled on either of the following conditions: * Neuron Chip in Operating mode and Comm Port in Differential mode. * Neuron Chip in Sleep mode and Comm Port in Differential mode and Comm Port Wake-up not masked. 14. Supported through an external oscillator only. 15. tcyc = 2(1/f), where f is the input clock (CLK1) frequency (10, 5, 2.5, 1.25, or 0.625 MHz). 16. Refer to Figure 3 for detailed measurement information. 17. The data hold parameter, tDHW, is measured to the disable levels shown in Figure 4, rather than to the traditional data invalid levels. 18. Refer to Figure 5 and Figure 4 for detailed measurement information.
Document #: 38-10002 Rev. *B
Page 9 of 16
PRELIMINARY
Differential Transceiver Electrical Characteristics
Characteristic at 3.3V Receiver Common Mode Voltage Range to maintain hysteresis[20] Receiver Common Mode Range to operate with unspecified hysteresis Input Offset Voltage Propagation Delay (F = 0, VID = Vhys/2 + 200 mV) Input Resistance Wake-up Time Differential Output Impedance for CP2 and CP3[21] Characteristic at 5V Receiver Common Mode Voltage Range to maintain hysteresis[20] Receiver Common Mode Range to operate with unspecified hysteresis Input Offset Voltage Propagation Delay (F = 0, VID = Vhys/2 + 200 mV) Input Resistance Wake-up Time Differential Output Impedance for CP2 and CP3[21] Min. 1.2 0.9 -0.05Vhys - 35 -- 5 -- Min. 0.6 0.4 -0.05Vhys - 35 -- 5 --
CY7C53120L8 CY7C53150L
Max. VDD - 1.5 VDD - 1.3 0.05Vhys + 35 230 ns -- 10 35 Max. VDD - 2.2 VDD - 1.75 0.05Vhys + 35 230 ns -- 10 35 Unit V V mV ns M s Unit V V mV ns M s
TEST SIGNAL CL = 20 pF for E CL = 30 pF for A0-A15, D0-D7, and R/W CL CL = 50 pF for all other signals
Figure 2. Signal Loading for Timing Specifications Unless Otherwise Specified
PWEH 2.0V 0.8V
PWEL 2.0V
Figure 3. Test Point Levels for E Pulse Width Measurements
DRIVE TO 2.4V DRIVE TO 0.4V
2.0V 0.8V A B 2.0V 0.8V
A -- Signal valid-to-signal valid specification (maximum or minimum) B -- Signal valid-to-signal invalid specification (maximum or minimum)
Figure 4. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified
Notes: 19. The three-state condition is when the device is not actively driving data. Refer to Figure 2 and Figure 5 for detailed measurement information. 20. Common mode voltage is defined as the average value of the waveform at each input at the time switching occurs. 21. Z0 = |V[CP2]-V[CP3] |/40 mA for 3.15 < VDD < 3.45V.
Document #: 38-10002 Rev. *B
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PRELIMINARY
VOH - 0.5 V
CY7C53120L8 CY7C53150L
VOL + 0.5 V VOH - Measured high output drive level VOL - Measured low output drive level
Figure 5. Test Point Levels for Driven-to-Three-State Time Measurements
TEST SIGNAL CL = 30 pF
VDD/2 ILOAD = 1.4 mA
Figure 6. Signal Loading for Driven-to-Three-State Time Measurements
tcyc E 20 pF Load PWEH PWEL
Address (A0 - A15) 30 pF Load
tAD Address
tAD Address tAH
tAD Address tAH
tAD Address tAH tAH
tRD R/W 30 pF Load tRH
tWR
tWH
tDSR Data (In) (D0 - D7) Data In tDHR
tDSR Data In tDHR tDDW tDHW Data Out tDDZ tDDW tDDZ tDHZ tDHW Data Out
Data (Out) (D0 - D7) 30 pF Load
tDHZ
Memory READ
Memory READ
Memory WRITE
Memory WRITE
Figure 7. External Memory Interface Timing Diagram
Document #: 38-10002 Rev. *B
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PRELIMINARY
Voltage
4
CY7C53120L8 CY7C53150L
V(CP0)
3
Time
Vcm
2
V(CP1) Voltage V(CP0)-V(CP1)
1
Vh
-1
Vtrip+ Vtrip-
Time
Neuron 5V Chip's Internal 0V Comparator Common-Mode voltage: Vcm = ( V(CP0) + V(CP1) ) / 2 Hysteresis Voltage: Vh = [Vtrip+] - [Vtrip-]
Figure 8. Differential Receiver Input Hysteresis Voltage Measurement Waveforms for 5V Operation
Voltage
3 2
V(CP0)
Time
Vcm
1
V(CP1) Voltage
0.5
V(CP0)-V(CP1) Vtrip+ VtripTime
Vh
-0.5
Neuron 3.3V Chip's Internal 0V Comparator Common-Mode voltage: Vcm = ( V(CP0) + V(CP1) ) / 2 Hysteresis Voltage: Vh = [Vtrip+] - [Vtrip-]
Figure 9. Differential Receiver Input Hysteresis Voltage Measurement Waveforms for 3.3V Operation
Document #: 38-10002 Rev. *B
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PRELIMINARY
Ordering Information
Part Number CY7C53150L-64AI CY7C53150L-100AI CY7C53120L8-32SI CY7C53120L8-44AI Flash (KB) 0.5 0.5 8 8 ROM (KB) 0 0 12 12 SRAM (KB) 4 4 4 4 Max. Input Clock (MHz) 20 20 20 20 Package Name A65 A100 S34 A44
CY7C53120L8 CY7C53150L
Package Type 64-lead Thin Plastic Quad Flat Pack 100-lead Thin Plastic Quad Flat Pack 32-lead (450 mil) Molded SOIC 44-lead Thin Plastic Quad Flat Pack
Package Diagrams
100-pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
Document #: 38-10002 Rev. *B
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PRELIMINARY
Package Diagrams (continued)
64-lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
CY7C53120L8 CY7C53150L
51-85046-*B
44-lead Thin Plastic Quad Flat Pack A44
51-85064-*B
Document #: 38-10002 Rev. *B
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PRELIMINARY
Package Diagrams (continued)
32-lead (450-mil) Molded SOIC S34
CY7C53120L8 CY7C53150L
51-85081-*A
Echelon, LonWorks, LonTalk, and Neuron are registered trademarks of Echelon Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-10002 Rev. *B
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
Document History Page
Document Title: CY7C53150L/CY7C53120L8 3.3V Neuron(R) Chip Network Processor Document Number: 38-10002 REV. ** *A ECN NO. 121963 123762 Issue Date 12/12/02 03/03/03 Orig. of Change PVO PVO New Data Sheet Changed Advance Information to Preliminary Added information on LVI, SCI/SPI, Reset Stretching Corrected values of ROM, Hysteresis, and IPU Added 100-pin TQFP pin definitions Made minor corrections to grammar and formatting Description of Change
CY7C53120L8 CY7C53150L
*B
125311
03/21/03
KBO
Add information on Power Sequence Corrected values of ROM Added default values of LVI, LVI filter and SPI divisor. Corrected Ipu Current limit values Clarified Reset Stretch times Corrected pin definitions (pins 10 to 14) on 100pin TQFP diagram Added Theta-JA value for the 100-pin TQFP package Changed part numbers to CY7C53120L8 / CY7C53150L Added ordering information table
Document #: 38-10002 Rev. *B
Page 16 of 16

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